SH7050 Datasheet, PDF (210/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
9.4.2
Example of DMA Transfer between External RAM and External Device with
DACK
In this example, an external request, serial address mode transfer with external memory as the
transfer source and an external device with DACK as the transfer destination is executed using
DMAC channel 1.
Table 9.8 indicates the transfer conditions and the setting values of each of the registers.
Table 9.8 Transfer Conditions and Register Set Values for Transfer between External
RAM and External Device with DACK
Transfer Conditions
Transfer source: external RAM
Transfer destination: external device with DACK
Transfer count: 32 times
Transfer source address: decremented
Transfer destination address: (setting ineffective)
Transfer request source: external pin (DREQ1) edge
detection
Bus mode: burst
Transfer unit: word
No interrupt request generation at end of transfer
Channel priority ranking: 2 > 0 > 1 > 3
Register
SAR1
DAR1
DMATCR1
CHCR1
DMAOR
Value
H'00400000
(access by DACK)
H'00000020
H'00002269
H'0201
9.4.3
Example of DMA Transfer between A/D Converter and Internal Memory (Address
Reload On)
In this example, the on-chip A/D converter channel 0 is the transfer source and internal memory is
the transfer destination, and the address reload function is on.
Table 9.9 indicates the transfer conditions and the setting values of each of the registers.
Rev. 5.00 Jan 06, 2006 page 190 of 818
REJ09B0273-0500