SH7050 Datasheet, PDF (671/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

21.5 Sleep Mode
Section 21 Power-Down State
21.5.1 Transition to Sleep Mode
Executing the SLEEP instruction when the SBY bit of SBYCR is 0 causes a transition from the
program execution state to the sleep mode. Although the CPU halts immediately after executing
the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip
peripheral modules continue to run during the sleep mode.
21.5.2 Canceling Sleep Mode
Cancellation by an Interrupt: When an interrupt occurs, the sleep mode is canceled and interrupt
exception processing is executed. The sleep mode is not canceled if the interrupt cannot be
accepted because its priority level is equal to or less than the mask level set in the CPU’s status
register (SR) or if an interrupt by an on-chip peripheral module is disabled at the peripheral
module.
Cancellation by a DMAC Address Error: If a DMAC address error occurs, the sleep mode is
canceled and DMAC address error exception processing is executed.
Cancellation by a Power-On Reset: A power-on reset resulting from setting the RES pin to low
level cancels the sleep mode.
Rev. 5.00 Jan 06, 2006 page 651 of 818
REJ09B0273-0500