SH7050 Datasheet, PDF (552/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 17 I/O Ports (I/O)
17.8.2 Port G Data Register (PGDR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PG15 PG14 PG13 PG12 PG11 PG10 PG9 PG8 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0
DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The port G data register (PGDR) is a 16-bit readable/writable register that stores port G data. Bits
PG15DR to PG0DR correspond to pins PG15/TIOB5/IRQ5 to PG0/ADTRG/IRQOUT.
When a pin functions as a general output, if a value is written to PGDR, that value is output
directly from the pin, and if PGDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PGDR is read the pin state, not the register value, is
returned directly. If a value is written to PGDR, although that value is written into PGDR it does
not affect the pin state. Table 17.14 summarizes port G data register read/write operations.
PGDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode or sleep mode.
Table 17.14 Port G Data Register (PGDR) Read/Write Operations
PGIOR
0
1
Pin Function
General input
Other than general
input
General output
Other than general
output
Read
Pin state
Pin state
PGDR value
PGDR value
Write
Value is written to PGDR, but does not affect
pin state
Value is written to PGDR, but does not affect
pin state
Write value is output from pin
Value is written to PGDR, but does not affect
pin state
Rev. 5.00 Jan 06, 2006 page 532 of 818
REJ09B0273-0500