SH7050 Datasheet, PDF (621/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 19 ROM (256 kB Version)
Bit 0—Program 2 (P2): Selects program mode transition or clearing (applicable addresses:
H'20000 to H'3FFFF). Do not set the ESU2, PSU2, EV2, PV2, or E2 bit at the same time.
Bit 0:
P2
0
1
Description
Program mode cleared
Transition to program mode
[Setting condition]
When FWE = 1, SWE = 1, and PSU2 = 1
(Initial value)
19.5.3 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other
blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not
set more than one bit. When on-chip flash memory is disabled, a read will return H'00, and writes
are invalid.
The flash memory block configuration is shown in table 19.3.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
EB3 EB2 EB1 EB0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R/W R/W R/W R/W
Rev. 5.00 Jan 06, 2006 page 601 of 818
REJ09B0273-0500