SH7050 Datasheet, PDF (55/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 2 CPU
Instruction Formats
d format
15
0
xxxx xxxx dddd dddd
Source
Operand
dddddddd:
Indirect GBR
with
displacement
R0(Direct
register)
dddddddd: PC
relative with
displacement
—
d12 format
—
15
0
xxxx dddd dddd dddd
Destination
Operand
R0 (Direct
register)
Example
MOV.L
@(disp,GBR),R0
dddddddd:
Indirect GBR with
displacement
R0 (Direct
register)
MOV.L
R0,@(disp,GBR)
MOVA
@(disp,PC),R0
dddddddd: PC
relative
dddddddddddd:
PC relative
BF
label
BRA label
(label = disp +
PC)
nd8 format
15
xxxx nnnn
dddd
0
dddd
dddddddd: PC
relative with
displacement
nnnn: Direct
register
MOV.L
@(disp,PC),Rn
i format
15
0
xxxx xxxx i i i i i i i i
ni format
15
0
xxxx nnnn i i i i i i i i
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
Indirect indexed
GBR
R0 (Direct
register)
—
nnnn: Direct
register
AND.B
#imm,@(R0,GBR)
AND #imm,R0
TRAPA #imm
ADD #imm,Rn
Note: * In multiply/accumulate instructions, nnnn is the source register.
Rev. 5.00 Jan 06, 2006 page 35 of 818
REJ09B0273-0500