SH7050 Datasheet, PDF (624/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 19 ROM (256 kB Version)
Bits 1 and 0—Flash Memory Area Selection (RAM1, RAM0): These bits are used together
with bit 2 to select the flash memory area to be overlapped with RAM. (See table 19.4.)
Table 19.4 Flash Memory Area Divisions
Addresses
H'FFD800–H'FFDBFF
H'03F000–H'03F3FF
H'03F400–H'03F7FF
H'03F800–H'03FBFF
H'03FC00–H'03FFFF
Block Name
RAM area 1 kB
EB8 (1 kB)
EB9 (1 kB)
EB10 (1 kB)
EB11 (1 kB)
RAMS
0
1
1
1
1
RAM1
*
0
0
1
1
RAM0
*
0
1
0
1
19.6 On-Board Programming Modes
When pins are set to on-board programming mode and a reset-start is executed, a transition is
made to the on-board programming state in which program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
19.5. For a diagram of the transitions to the various flash memory modes, see figure 19.2.
Table 19.5 Setting On-Board Programming Modes
Mode
Boot mode Expanded mode
Single chip mode
Expanded mode
Single chip mode
Expanded mode
Single chip mode
User program Expanded mode
mode
Single chip mode
Expanded mode
Single chip mode
Expanded mode
Single chip mode
PLL Multiple FWE
×1
1
×2
×4
×1
1
×2
×4
MD3
0
0
0
0
1
1
0
0
0
0
1
1
MD2
0
0
1
1
0
0
0
0
1
1
0
0
MD1
0
0
0
0
0
0
1
1
1
1
1
1
MD0
0
1
0
1
0
1
0
1
0
1
0
1
Rev. 5.00 Jan 06, 2006 page 604 of 818
REJ09B0273-0500