SH7050 Datasheet, PDF (359/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Contention between DCNT Write and Counter Clearing by Underflow: With the channel 10
down-counters (DCNT10A to DCNT10H), if the count is halted due to underflow occurring in the
T2 state of a down-counter write cycle by the CPU, retention of the H'0000 value has priority and
the write to DCNT by the CPU is not performed. Writing of 1 to the interrupt status flag (OSF)
when the underflow occurs is performed in the same way as for normal underflow.
The timing in this case is shown in figure 10.63. In this example, a write of H'5555 to DCNT is
attempted at the same time as DCNT underflows.
T1
T2
CK
DCNT input clock
Address
DCNT address
Write data
5555
Internal write signal
Underflow signal
DCNT 0001
0000
H'0000 retained when DCNT halts
0000
Interrupt status flag
(OSF)
Figure 10.63 Contention between DCNT Write and Underflow
Rev. 5.00 Jan 06, 2006 page 339 of 818
REJ09B0273-0500