SH7050 Datasheet, PDF (554/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 17 I/O Ports (I/O)
17.9.2 Port H Data Register (PHDR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PH15 PH14 PH13 PH12 PH11 PH10 PH9 PH8 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0
DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR DR
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
The port H data register (PHDR) is a 16-bit read-only register that stores port H data. Bits
PH15DR to PH0DR correspond to pins PH15/AN15 to PH0/AN0.
Writes to these bits are ignored, and do not affect the pin states. When these bits are read, the pin
state, not the register value, is returned directly. However, 1 will be returned while A/D converter
analog input is being sampled. Table 17.16 summarizes port H data register read/write operations.
PHDR is not initialized by a power-on reset, or in hardware standby mode, software standby
mode, or sleep mode. (The bits always reflect the pin states.)
Table 17.16 Port H Data Register (PHDR) Read/Write Operations
Pin Input/Output
Input
n = 0 to 15
Pin Function
General input
ANn
Read
Pin state is read
1 is read
Write
Ignored (does not affect pin state)
Ignored (does not affect pin state)
17.10 POD (Port Output Disable)
The output port drive buffers for the address bus pins (A20 to A0) and data bus pins (D15 to D0)
can be controlled by the POD (port output disable) pin input level. However, this function is
enabled only when the address bus pins (A20 to A0) and data bus pins (D15 to D0) are designated
as general output ports.
Output buffer control by means of POD is performed asynchronously from bus cycles.
POD
0
1
Address Bus Pins (A20 to A0) and Data Bus Pins (D15 to D0)
(when Designated as Output Ports)
Enabled (high-impedance)
Disabled (general output)
Rev. 5.00 Jan 06, 2006 page 534 of 818
REJ09B0273-0500