SH7050 Datasheet, PDF (679/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 22 Electrical Characteristics
22.3.2 Control Signal Timing
Table 22.5 Control Signal Timing
Conditions: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, AV_ref = 4.5 V to AV_CC, V_SS = AV_SS = 0 V,
Ta = –40 to +85°C
Item
Symbol Min Max Unit Figure
RES pulse width
t
RESW
20
—
t
22.4
cyc
RES setup time
NMI setup time^*
IRQ7–IRQ0 setup time (edge detection)^*
IRQ7–IRQ0 setup time (level detection)^*
t_RESS
t_NMIS
t_IRQES
t
IRQLS
30
—
ns
30
—
ns
22.4, 22.5
30
—
ns
30
—
ns
NMI hold time
t_NMIH
50
—
ns
22.5
IRQ7–IRQ0 hold time
t_IRQEH
30
—
ns
IRQOUT hold time
t_IRQOD
—
25 ns 22.6
Bus request setup time
t_BRQS
30
—
ns
22.7
Bus acknowledge delay time 1
t
BACKD1
—
25 ns
Bus acknowledge delay time 2
t
BACKD2
—
25 ns
Bus three-state delay time
t
—
50 ns
BZD
Note: * The RES, NMI, and IRQ7–IRQ0 signals are asynchronous inputs, but when the setup
times shown here are provided, the signals are considered to have produced changes
at clock fall. If the setup times are not provided, recognition is delayed until the next
clock rise or fall.
CK
RES
t_RESS
t_RESS
V_IH
V_IL
V_IH
V_IL
t_RESW
Figure 22.4 Reset Input Timing
Rev. 5.00 Jan 06, 2006 page 659 of 818
REJ09B0273-0500