SH7050 Datasheet, PDF (327/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
IMF (ICF) Setting Timing in Compare-Match: The IMF bit (CMF bit in case of channels 6 to
9) is set to 1 in the timer status register (TSR) by the compare-match signal generated when the
general register (GR) or cycle register (CYLR) value matches the timer counter (TCNT) value.
The compare-match signal is generated in the last state of the match (when the matched TCNT
count value is updated).
The timing in this case is shown in figure 10.31.
CK
TCNT input clock
TCNT
N
N+1
GR(CYLR)
N
Compare-match signal
Interrupt status flag
IMF (CMF)
Interrupt request signal
IMI (CMI)
Figure 10.31 IMF (CMF) Setting Timing in Compare-Match
Rev. 5.00 Jan 06, 2006 page 307 of 818
REJ09B0273-0500