SH7050 Datasheet, PDF (466/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 14 A/D Converter
14.2.6 A/D Trigger Register (ADTRGR)
The A/D trigger register (ADTRGR) is an 8-bit readable/writable register that selects the A/D0
trigger. Either external pin (ADTRG) or ATU (ATU interval timer interrupt) triggering can be
selected.
ADTRGR is initialized to H'FF by a power-on reset, and in hardware standby mode and software
standby mode.
Bit: 7
6
5
4
3
2
1
0
EXTRG —
—
—
—
—
—
—
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W
R
R
R
R
R
R
R
Bit 7—Trigger Enable (EXTRG): Selects external pin input (ADTRG) or the ATU interval
timer interrupt.
Bit 7:
EXTRGA
0
1
Description
A/D conversion is triggered by the ATU channel 0 interval timer interrupt
A/D conversion is triggered by external pin input (ADTRG)
(Initial value)
Bits 6 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
In order to select external triggering or ATU triggering, the TGRE bit in ADCR0 must be set to 1.
For details, see section 14.2.3, A/D Control Register 0.
Rev. 5.00 Jan 06, 2006 page 446 of 818
REJ09B0273-0500