SH7050 Datasheet, PDF (634/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 19 ROM (256 kB Version)
Start
*1
Set SWE bit in FLMCR1
Wait (10) µs
n=1
Set EBR1(2)
*3
Enable WDT
Set ESU1(2) bit in FLMCR1(2)
Wait (200) µs
Set E1(2) bit in FLMCR1(2)
Wait (5) ms
Clear E1(2) bit in FLMCR1(2)
Wait (10) µs
Clear ESU1(2) bit in FLMCR1(2)
Wait (10) µs
Disable WDT
Set EV1(2) bit in FLMCR1(2)
Wait (20) µs
Start erase
Halt erase
Set block start address to verify address
n←n+1
H'FF dummy write to verify address
Wait (2) µs
Increment
address
NG
Read verify data
*2
NG
Verify data = all "1"?
OK
Last address of block?
OK
Clear EV1(2) bit in FLMCR1(2)
Clear EV1(2) bit in FLMCR1(2)
Wait (5) µs
Wait (5) µs
NG ^*4
End of
erasing of all erase
blocks?
OK
Clear SWE bit in FLMCR1
NG
n ≥ 61?
OK
Clear SWE bit in FLMCR1
End of erasing
Erase failure
Notes: 1. Preprogramming (setting erase block data to all “0”) is not necessary.
2. Verify data is read in 32-bit (longword) units.
3. Set only one bit in EBR1(2). More than one bit cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
Figure 19.8 Erase/Erase-Verify Flowchart
Rev. 5.00 Jan 06, 2006 page 614 of 818
REJ09B0273-0500