SH7050 Datasheet, PDF (354/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Contention between DTR Write and BFR Value transfer by Buffer Function: Do not write to
the duty register (DTR) when the free-running counter (TCNT) has been started in channels 6 to 9.
If there is contention between transfer of the buffer register (BFR) value to the corresponding
DTR due to a cycle register compare-match, and a write to DTR by the CPU, the OR of the BFR
value and CPU write value is written to DTR.
Figure 10.58 shows an example in which contention arises when the BFR value is H'AAAA and
the value to be written to DTR is H'5555.
CK
Address
Internal write signal
Compare-match signal
DTR address
H'5555
written
to DTR
BFR
H'AAAA
DTR
H'FFFF
(OR of H'5555 and
H'AAAA)
Figure 10.58 Contention between DTR Write and BFR Value Transfer by Buffer Function
Rev. 5.00 Jan 06, 2006 page 334 of 818
REJ09B0273-0500