SH7050 Datasheet, PDF (325/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.3.17 Timing of Buffer Register (BFR) Write and Transfer by Buffer Function
In channels 6 to 9, if the BFR value is transferred to the duty register (DTR) by a compare-match
with the cycle register (CYLR) in the T2 state during a write cycle from the CPU to the buffer
register (BFR), the value prior to the CPU write to BFR is transferred to DTR.
The timing in this case is shown in figure 10.29. In this example, a CYLR compare-match and a
write of H'AAAA to BFR occur simultaneously when the BFR value is H'5555.
BFR write cycle
T1
T2
CK
Address
Internal write signal
Compare-match signal
BFR address
H'AAAA
written
to BFR
BFR
H'5555
H'AAAA
DTR
H'5555
Figure 10.29 Contention between Buffer Register (BFR) Write and Transfer by Buffer
Function
Rev. 5.00 Jan 06, 2006 page 305 of 818
REJ09B0273-0500