SH7050 Datasheet, PDF (277/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 1—Input Capture/Compare-Match Interrupt Enable (IME2B): Enables or disables
interrupt requests by IMF2B in TSR when IMF2B is set to 1.
Bit 1:
IME2B
0
1
Description
IMI2B interrupt requested by IMF2B is disabled
IMI2B interrupt requested by IMF2B is enabled
(Initial value)
Bit 0—Input Capture/Compare-Match Interrupt Enable (IME2A): Enables or disables
interrupt requests by IMF2A in TSR when IMF2A is set to 1.
Bit 0:
IME2A
0
1
Description
IMI2A interrupt requested by IMF2A is disabled
IMI2A interrupt requested by IMF2A is enabled
(Initial value)
Timer Interrupt Enable Registers DH and DL (TIERDH, TIERDL)
TIERDH controls enabling/disabling of channel 3 input capture, compare-match, and overflow
interrupt requests.
Bit: 7
6
5
4
3
2
1
0
—
—
— OVE3 IME3D IME3C IME3B IME3A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W R/W R/W R/W R/W
Bits 7 to 5—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 4—Overflow Interrupt Enable (OVE3): Enables or disables interrupt requests by OVF3 in
TSR when OVF3 is set to 1.
Bit 4:
OVE3
0
1
Description
OVI3 interrupt requested by OVF3 is disabled
OVI3 interrupt requested by OVF3 is enabled
(Initial value)
Rev. 5.00 Jan 06, 2006 page 257 of 818
REJ09B0273-0500