SH7050 Datasheet, PDF (316/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
An example of channel 6 to 9 PWM operation is shown in figure 10.20.
In the example in figure 10.20, H'F000 is set in CYLR6 to CYLR8, H'F000 in DTR6, H'7000 in
DTR7, and H'0000 in DTR8, ATU channels 6 to 8 are activated simultaneously, and waveform
output (100%, 50%, 0%) is generated on external pins TO6 to TO8.
H'FFFF
CYLR6–8,
DTR6 (H'F000)
DTR7 (H'7000)
DTR8 (H'0000)
Counter value
TCNT6 to TCNT8
No change
Time
No change
TO6
TO7
No change
No change
No change
TO8 (‘0’)
Figure 10.20 Example of PWM Waveform Output Operation
In ATU channels 3 to 5, when PWM mode is set, corresponding general register GR3D, GR4D,
and GR5B function as cycle registers, and GR3A to GR3C, GR4A to GR4C, and GR5A, as duty
registers. At the same time, external pins TIOA3 to TIOC3, TIOA4 to TIOC4, and TIOA5
function as PWM waveform output pins. In channels 3 and 4, there are four duty registers for one
cycle register, and the cycle is the same for all the corresponding output pins.
In PWM mode, output of a 0% duty waveform cannot be set for ATU channels 3 to 5. If 0% duty
is required, channels 6 to 9 should be used. Although constant 1 output is performed if 100% duty
is set (GR3A, B, C ≥ GR3D, GR4A, B, C ≥ GR4D or GR5A ≥ GR5B), use of channels 6 to 9 is
also recommended if 100% duty is to be set.
An example of channel 3 to 5 PWM operation is shown in figure 10.21.
Rev. 5.00 Jan 06, 2006 page 296 of 818
REJ09B0273-0500