SH7050 Datasheet, PDF (223/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Block Diagram of Channel 2: Figure 10.4 shows a block diagram of ATU channel 2.
TSTR
TCLKA
TCLKB
φ/(m·2ⁿ)
1 ≤ m ≤ 32
0≤n≤5
Clock selection
Comparator
Control logic
APCHIGH
APCLOW
OVI2
IMI2A
IMI2B
TIOA2
TIOB2
OFF2A–2B
Module data bus
Legend:
TSTR: Timer start register (16 bits)
TCR2: Timer control register 2 (8 bits)
TIOR2A: Timer I/O control register 2 (8 bits)
TSRC: Timer status register C (8 bits)
TIERC: Timer interrupt enable register C (8 bits)
TCNT2: Free-running counter 2 (16 bits)
GR2: General register 2 (16 bits)
Interrupts:
OVI2: Overflow interrupt 2
IMI2: Input capture/compare-match interrupt 2
Inter-channel connection signal:
OFF2: Offset compare-match signal
Inter-module connection signals:
APCHIGH: GR2B compare-match signal
APCLOW: GR2A compare-match signal
Figure 10.4 Block Diagram of Channel 2
Rev. 5.00 Jan 06, 2006 page 203 of 818
REJ09B0273-0500