SH7050 Datasheet, PDF (390/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 13 Serial Communication Interface (SCI)
• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-
error interrupts are requested independently. The transmit-data-empty and receive-data-full
interrupts can start the direct memory access controller (DMAC)/data transfer controller
(DTC) to transfer data.
13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the SCI.
Module data bus
RxD
TxD
SCK
RDR
TDR
SSR
BRR
SCR
RSR
TSR
SMR
Transmit/
receive control
Baud rate
generator
Parity
generation
Clock
Parity check
External clock
SCI
RSR: Receive shift register
RDR: Receive data register
TSR : Transmit shift register
TDR : Transmit data register
SMR: Serial mode register
SCR : Serial control register
SSR : Serial status register
BRR : Bit rate register
Figure 13.1 SCI Block Diagram
Internal
data bus
φ
φ/4
φ/16
φ/64
TEI
TxI
RxI
ERI
Rev. 5.00 Jan 06, 2006 page 370 of 818
REJ09B0273-0500