SH7050 Datasheet, PDF (129/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 8 Bus State Controller (BSC)
Section 8 Bus State Controller (BSC)
8.1 Overview
The bus state controller (BSC) divides up the address spaces and outputs control for various types
of memory. This enables memories like SRAM, and ROM to be linked directly to the LSI without
external circuitry.
8.1.1 Features
The BSC has the following features:
• Address space is divided into four spaces
 A maximum linear 2 Mbytes for on-chip ROM effective mode, and a maximum linear
4-Mbyte for on-chip ROM ineffective mode for address space CS0
 A maximum linear 4 Mbytes for each of the address spaces CS1–CS3
 Bus width can be selected for each space (8 or 16 bits)
 Wait states can be inserted by software for each space
 Wait state insertion with WAIT pin in external memory space access
 Outputs control signals for each space according to the type of memory connected
• On-chip ROM and RAM interfaces
 On-chip RAM access of 32 bits in 1 state
Rev. 5.00 Jan 06, 2006 page 109 of 818
REJ09B0273-0500