SH7050 Datasheet, PDF (458/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 14 A/D Converter
Table 14.3 Analog Input Channels and A/D Data Registers
Analog
Input
Channel
AN0
AN1
AN2
AN3
A/D Data
Register
ADDR0
ADDR1
ADDR2
ADDR3
Analog
Input
Channel
AN4
AN5
AN6
AN7
A/D Data
Register
ADDR4
ADDR5
ADDR6
ADDR7
Analog
Input
Channel
AN8
AN9
AN10
AN11
A/D Data
Register
ADDR8
ADDR9
ADDR10
ADDR11
Analog
Input
Channel
AN12
AN13
AN14
AN15
A/D Data
Register
ADDR12
ADDR13
ADDR14
ADDR15
14.2.2 A/D Control/Status Register 0 (ADCSR0)
A/D control/status register 0 (ADCSR0) is an 8-bit readable/writable register whose functions
include selection of the A/D conversion mode for A/D0.
ADCSR0 is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Bit: 7
6
5
4
ADF ADIE ADM1 ADM0
Initial value: 0
0
0
0
R/W: R/(W)* R/W R/W R/W
Note: * Only 0 can be written, to clear the flag.
3
CH3
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7:
ADF
0
1
Description
Indicates that A/D0 is performing A/D conversion, or is in the idle state. (Initial value)
[Clearing conditions]
• When ADF is read while set to 1, then 0 is written in ADF
• When the DMAC is activated by ADI0
Indicates that A/D0 has finished A/D conversion, and the digital value has been
transferred to ADDR.
[Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When all A/D conversions end within one selected analog group
Rev. 5.00 Jan 06, 2006 page 438 of 818
REJ09B0273-0500