SH7050 Datasheet, PDF (171/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Figure 9.2 is a flowchart of this procedure.
Start
Initial settings
(SAR, DAR, TCR, CHCR, DMAOR)
DE, DME = 1 and
No
NMIF, AE, TE = 0?
Yes
Transfer request
No
occurs?^*1
Yes
Transfer (1 transfer unit);
DMATCR – 1 → DMATCR, SAR and DAR
updated
*2
Bus mode,
*3
transfer request mode,
DREQ detection selection
system
No
DMATCR = 0?
Yes
DEI interrupt request (when IE = 1)
Does
NMIF = 1, AE = 1,
No
DE = 0, or DME
= 0?
Yes
Transfer aborted
Does
NMIF = 1, AE = 1,
No
DE = 0, or DME
= 0?
Yes
Transfer ends
Normal end
Notes: 1.
2.
3.
In auto-request mode, transfer begins when NMIF, AE, and TE are all 0,
and the DE and DME bits are set to 1.
DREQ = level detection in burst mode (external request) or cycle-steal
mode.
DREQ = edge detection in burst mode (external request), or auto-request
mode in burst mode.
Figure 9.2 DMAC Transfer Flowchart
Rev. 5.00 Jan 06, 2006 page 151 of 818
REJ09B0273-0500