SH7050 Datasheet, PDF (63/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 2 CPU
Instruction
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT
Rn
EXTS.B Rm,Rn
EXTS.W Rm,Rn
EXTU.B Rm,Rn
EXTU.W Rm,Rn
MAC.L @Rm+,@Rn+
MAC.W @Rm+,@Rn+
MUL.L Rm,Rn
MULS.W Rm,Rn
MULU.W Rm,Rn
NEG
NEGC
Rm,Rn
Rm,Rn
Instruction Code
0011nnnnmmmm1101
0011nnnnmmmm0101
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm1111
0100nnnnmmmm1111
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
Operation
Signed operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bit
Unsigned operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bit
Rn – 1 → Rn, when Rn
is 0, 1 → T. When Rn
is nonzero, 0 → T
A byte in Rm is sign-
extended → Rn
A word in Rm is sign-
extended → Rn
A byte in Rm is zero-
extended → Rn
A word in Rm is zero-
extended → Rn
Signed operation of
(Rn) × (Rm) + MAC →
MAC 32 × 32 + 64 →
64 bit
Signed operation of
(Rn) × (Rm) + MAC →
MAC 16 × 16 + 64 →
64 bit
Rn × Rm → MACL,
32 × 32 → 32 bit
Signed operation of
Rn × Rm → MAC
16 × 16 → 32 bit
Unsigned operation of
Rn × Rm → MAC
16 × 16 → 32 bit
0–Rm → Rn
0–Rm–T → Rn, Borrow
→T
Execu-
tion
Cycles
2 to 4^*
2 to 4^*
1
1
1
1
1
3/
(2 to 4)^*
3/(2)^*
2 to 4^*
1 to 3^*
1 to 3^*
1
1
T Bit
—
—
Comparison
result
—
—
—
—
—
—
—
—
—
—
Borrow
Rev. 5.00 Jan 06, 2006 page 43 of 818
REJ09B0273-0500