SH7050 Datasheet, PDF (659/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 20 RAM
Section 20 RAM
20.1 Overview
The SH7050 has 6 kbytes/the SH7051 has 10 kbytes of on-chip RAM. The on-chip RAM is linked
to the CPU and direct memory access controller (DMAC) with a 32-bit data bus (figure 20.1). The
CPU can access data in the on-chip RAM in 8, 16, or 32 bit widths. The DMAC can access 8 or 16
bit widths. On-chip RAM data can always be accessed in one state, making the RAM ideal for use
as a program area, stack area, or data area, which require high-speed access. The contents of the
on-chip RAM are held in both the sleep and software standby modes. When the RAME bit (see
below) is cleared to 0, the on-chip RAM contents are also held in hardware standby mode.
Memory area 0 addresses H'FFFFF800 to H'FFFFFFFF (SH7050) and H'FFFF0800 to
H'FFFFFFFF (SH7051) are allocated to the on-chip RAM.
SH7050
Internal data bus (32 bits)
H'FFFFF800
H'FFFFF804
H'FFFFF801
H'FFFFF805
H'FFFFF802
H'FFFFF806
H'FFFFF803
H'FFFFF807
On-chip RAM
SH7051
H'FFFFFFFC H'FFFFFFFD H'FFFFFFFE H'FFFFFFFF
Internal data bus (32 bits)
H'FFFFD800
H'FFFFD804
H'FFFFD801
H'FFFFD805
H'FFFFD802
H'FFFFD806
H'FFFFD803
H'FFFFD807
On-chip RAM
H'FFFFFFFC H'FFFFFFFD H'FFFFFFFE H'FFFFFFFF
Figure 20.1 Block Diagram of RAM
Rev. 5.00 Jan 06, 2006 page 639 of 818
REJ09B0273-0500