SH7050 Datasheet, PDF (56/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 2 CPU
2.4 Instruction Set by Classification
Table 2.10 Classification of Instructions
Operation
Classification Types Code
Function
No. of
Instructions
Data transfer 5
MOV
Data transfer, immediate data transfer,
39
peripheral module data transfer, structure
data transfer
MOVA
Effective address transfer
MOVT
T bit transfer
SWAP
Swap of upper and lower bytes
XTRCT Extraction of the middle of registers connected
Arithmetic
21
ADD
Binary addition
33
operations
ADDC
Binary addition with carry
ADDV
Binary addition with overflow check
CMP/cond Comparison
DIV1
Division
DIV0S
Initialization of signed division
DIV0U
Initialization of unsigned division
DMULS Signed double-length multiplication
DMULU Unsigned double-length multiplication
DT
Decrement and test
EXTS
Sign extension
EXTU
Zero extension
MAC
Multiply/accumulate, double-length
multiply/accumulate operation
MUL
Double-length multiply operation
MULS
Signed multiplication
MULU
Unsigned multiplication
NEG
Negation
NEGC
Negation with borrow
SUB
Binary subtraction
SUBC
Binary subtraction with borrow
SUBV
Binary subtraction with underflow
Rev. 5.00 Jan 06, 2006 page 36 of 818
REJ09B0273-0500