SH7050 Datasheet, PDF (540/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 17 I/O Ports (I/O)
17.3.1 Register Configuration
The port B register is shown in table 17.3.
Table 17.3 Port B Register
Name
Abbreviation R/W Initial Value Address
Port B data register
PBDR
R/W H'C0C0
H'FFFF8386
Note: A register access is performed in two cycles regardless of the access size.
Access Size
8, 16
17.3.2 Port B Data Register (PBDR)
Bit: 15
—
Initial value: 1
R/W: R
14 13 12 11 10 9 8 7
—
PB11 PB10 PB9
DR DR DR
PB8
DR
PB7
DR
PB6
DR
—
10000001
R R/W R/W R/W R/W R/W R/W R
6543210
—
PB5 PB4 PB3 PB2 PB1 PB0
DR DR DR DR DR DR
1000000
R R/W R/W R/W R/W R/W R/W
The port B data register (PBDR) is a 16-bit readable/writable register that stores port B data. Bits
PB11DR to PB0DR correspond to pins PB11/A21/POD to PB0/TO6.
When a pin functions as a general output, if a value is written to PBDR, that value is output
directly from the pin, and if PBDR is read, the register value is returned directly regardless of the
pin state. For PB6 to PB10, when the POD pin is driven low, general outputs go to the high-
impedance state regardless of the PBDR value. When the POD pin is driven high, the written
value is output from the pin.
When a pin functions as a general input, if PBDR is read the pin state, not the register value, is
returned directly. If a value is written to PBDR, although that value is written into PBDR it does
not affect the pin state. Table 17.4 summarizes port B data register read/write operations.
PBDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode or sleep mode.
Rev. 5.00 Jan 06, 2006 page 520 of 818
REJ09B0273-0500