SH7050 Datasheet, PDF (488/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 15 Compare Match Timer (CMT)
15.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared either by writing a 0 to it after reading a 1, or by a
clear signal after a DTC transfer. Figure 15.5 shows the timing when the CMF bit is cleared by the
CPU.
CMCSR write cycle
T₁
T₂
CK
CMF
Figure 15.5 Timing of CMF Clear by the CPU
Rev. 5.00 Jan 06, 2006 page 468 of 818
REJ09B0273-0500