SH7050 Datasheet, PDF (568/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 18 ROM (128 kB Version)
18.5.3 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit readable/writable register that specifies the flash memory erase area block by
block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby
mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin
and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block
can be erased. Other blocks are erase-protected. Set only one bit in EBR1 (more than one bit
cannot be set). When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
The flash memory block configuration is shown in table 18.3.
Bit: 7
6
5
4
3
2
1
0
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 18.3 Flash Memory Erase Blocks
Block (Size)
EB0 (32 kB)
EB1 (32 kB)
EB2 (32 kB)
EB3 (28 kB)
EB4 (1 kB)
EB5 (1 kB)
EB6 (1 kB)
EB7 (1 kB)
Address
H'000000–H'007FFF
H'008000–H'00FFFF
H'010000–H'017FFF
H'018000–H'01EFFF
H'01F000–H'01F3FF
H'01F400–H'01F7FF
H'01F800–H'01FBFF
H'01FC00–H'01FFFF
Rev. 5.00 Jan 06, 2006 page 548 of 818
REJ09B0273-0500