SH7050 Datasheet, PDF (313/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

ATU
Section 10 Advanced Timer Unit (ATU)
Upper 4 bits
of ITVRR
13 12 11 10 bit
TCNT0L
(32 bit FRT)
Edge sensor
Lower 4 bits
of ITVRR
TRSAH
(status flags)
A/D converter
activation signal
INTC
Figure 10.17 Schematic Diagram of Interval Timer
An example of TCNT0 and bit detection operation is shown in figure 10.18.
In the example in figure 10.18, free-running counter 0 (TCNT0) is started by setting 1 in ITVE1 in
ITVRR.
Rev. 5.00 Jan 06, 2006 page 293 of 818
REJ09B0273-0500