SH7050 Datasheet, PDF (377/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 12 Watchdog Timer (WDT)
12.1.4 Register Configuration
Table 12.2 summarizes the three WDT registers. They are used to select the clock, switch the
WDT mode, and control the reset signal.
Table 12.2 WDT Registers
Address
Name
Abbreviation R/W
Initial Value Write^*1
Read^*2
Timer control/status TCSR
register
R/(W)^*3 H'18
H'FFFF8610 H'FFFF8610
Timer counter
TCNT
Reset control/status RSTCSR
register
R/W
H'00
R/(W)^*3 H'1F
H'FFFF8612
H'FFFF8611
H'FFFF8613
Notes: In register access, three cycles are required for both byte access and word access.
1. Write by word transfer. It cannot be written in byte or longword.
2. Read by byte transfer. It cannot be read in word or longword.
3. Only 0 can be written in bit 7 to clear the flag.
12.2 Register Descriptions
12.2.1 Timer Counter (TCNT)
The TCNT is an 8-bit read/write upcounter. (The TCNT differs from other registers in that it is
more difficult to write to. See section 12.2.4, Register Access, for details.) When the timer enable
bit (TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts
counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in the
TCSR. When the value of the TCNT overflows (changes from H'FF to H'00), a watchdog timer
overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode
selected in the WT/IT bit of the TCSR.
The TCNT is initialized to H'00 by a power-on reset and when the TME bit is cleared to 0. It is not
initialized in the standby mode.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.00 Jan 06, 2006 page 357 of 818
REJ09B0273-0500