SH7050 Datasheet, PDF (332/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Clearing by DMAC: The interrupt status flag (ICF0B, CMF6) is cleared automatically during
data transfer when the DMAC is activated by input capture (ICR0B) or compare-match (CYLR6).
The procedure and timing in this case are shown in figure 10.36.
CK
Start
Clear request signal
from DMAC
Activate DMAC
Interrupt status
flag clear signal
Interrupt status flag
Interrupt status
ICF0B, CMF6
flag cleared during
data transfer
Interrupt request
signal
Figure 10.36 Procedure and Timing for Clearing by DMAC
Rev. 5.00 Jan 06, 2006 page 312 of 818
REJ09B0273-0500