SH7050 Datasheet, PDF (386/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 12 Watchdog Timer (WDT)
12.4 Notes on Use
12.4.1 TCNT Write and Increment Contention
If a timer counter increment clock pulse is generated during the T₃ state of a write cycle to the
TCNT, the write takes priority and the timer counter is not incremented (figure 12.8).
TCNT write cycle
T₁
T₂
T₃
CK
Address
TCNT address
Internal
write signal
TCNT
input clock
TCNT
N
M
Counter write data
Figure 12.8 Contention between TCNT Write and Increment
12.4.2 Changing CKS2 to CKS0 Bit Values
If the values of bits CKS2 to CKS0 are altered while the WDT is running, the count may
increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of bits CKS2 to CKS0.
12.4.3 Changing between Watchdog Timer/Interval Timer Modes
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)
before switching between interval timer mode and watchdog timer mode.
Rev. 5.00 Jan 06, 2006 page 366 of 818
REJ09B0273-0500