SH7050 Datasheet, PDF (667/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 21 Power-Down State
Oscillator
RES
HSTBY
RES pulse
width t_RESW
Oscillation
stabilization
time
Figure 21.1 Hardware Standby Mode Timing
Reset
exception
handling
21.4 Software Standby Mode
21.4.1 Transition to Software Standby Mode
To enter the standby mode, set the SBY bit to 1 in SBYCR, then execute the SLEEP instruction.
The LSI moves from the program execution state to the standby mode. In the standby mode,
power consumption is greatly reduced by halting not only the CPU, but the clock and on-chip
peripheral modules as well. CPU register contents and on-chip RAM data are held as long as the
prescribed voltages are applied (when the RAME bit in SYSCR is 0). The register contents of
some on-chip peripheral modules are initialized, but some are not (table 21.4). The I/O port status
can be selected as held or high impedance by the port high impedance bit (HIZ) of the SBYCR.
For pin status other than for the I/O port, refer to Appendix B, Pin States.
Rev. 5.00 Jan 06, 2006 page 647 of 818
REJ09B0273-0500