SH7050 Datasheet, PDF (345/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5 ): An example of the
setup procedure for PWM timer operation (channels 3 to 5 ) is shown in figure 10.51.
1. Set the first-stage counter clock φ' in prescaler register 1 (PSCR1), and select the second-stage
counter clock φ" with the CKSEL bit in the timer control register (TCR). When selecting an
external clock, at the same time select the external clock edge type with the CKEG bit in TCR.
2. Set the port E control register (PECR) or port G control register (PGCR), corresponding to the
waveform output port, to ATU output compare-match output. Also set the corresponding bit to
1 in the port E IO register (PEIOR) or port G IO register (PGIOR) to specify the output
attribute.
3. Set bit T3PWM–T5PWM in the timer mode register (TMDR) to PWM mode. When PWM
mode is set, the TIOD3. TIOD4, and TIOD5 pins go to 0 output irrespective of the timer I/O
control register (TIOR) contents.
4. The GR3A–GR3C, GR4A–GR4C, and GR5A ATU general registers are used as duty registers
(DTR), and the GR3D, GR4D, and GR5B ATU general registers as cycle registers (CYLR).
Set the PWM waveform output 0 output timing in DTR, and the PWM waveform output 1
output timing in CYLR.
5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running
counter (TCNT) for the relevant channel.
Rev. 5.00 Jan 06, 2006 page 325 of 818
REJ09B0273-0500