SH7050 Datasheet, PDF (738/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Timer Status Register AH
(TSRAH)
H'FFFF8283 (Channel 0) 8
ATU
Bit: 7
6
5
4
Bit name: —
—
—
—
Initial value: 0
0
0
0
R/W: R
R
R
R
Note: * Only 0 can be written to clear the flag.
3
IIF3
0
R/(W)*
2
IIF2
0
R/(W)*
1
IIF1
0
R/(W)*
0
IIF0
0
R/(W)*
Bit
Bit Name
Value Description
3
Interval interrupt flag
0
[Clearing condition]
(Initial value)
(IIF3)
Read IIF3 when IIF3 =1, then write 0 in IIF3
1
[Setting condition]
When 1 is generated by AND of ITVE3 in ITVRR
and bit 13 of TCNT0L
2
Interval interrupt flag
0
[Clearing condition]
(Initial value)
(IIF2)
Read IIF2 when IIF2 =1, then write 0 in IIF2
1
[Setting condition]
When 1 is generated by AND of ITVE2 in ITVRR
and bit 12 of TCNT0L
1
Interval interrupt flag
0
[Clearing condition]
(Initial value)
(IIF1)
Read IIF1 when IIF1 =1, then write 0 in IIF1
1
[Setting condition]
When 1 is generated by AND of ITVE1 in ITVRR
and bit 11 of TCNT0L
0
Interval interrupt flag
0
[Clearing condition]
(Initial value)
(IIF0)
Read IIF0 when IIF0 =1, then write 0 in IIF0
1
[Setting condition]
When 1 is generated by AND of ITVE0 in ITVRR
and bit 10 of TCNT0L
Rev. 5.00 Jan 06, 2006 page 718 of 818
REJ09B0273-0500