SH7050 Datasheet, PDF (178/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
9.3.4 DMA Transfer Types
The DMAC supports the transfers shown in table 9.5. It can operate in the single address mode, in
which either the transfer source or destination is accessed using an acknowledge signal, or dual
address mode, in which both the transfer source and destination addresses are output. The dual
address mode consists of a direct address mode, in which the output address value is the object of
a direct data transfer, and an indirect address mode, in which the output address value is not the
object of the data transfer, but the value stored at the output address becomes the transfer object
address. The actual transfer operation timing varies with the bus mode. The DMAC has two bus
modes: cycle-steal mode and burst mode.
Table 9.5 Supported DMA Transfers
Transfer Destination
Transfer
Source
External
Device with
DACK
External
Memory
Memory-
Mapped
External
Device
On-Chip
Memory
On-Chip
Peripheral
Module
External Not available
device with
DACK
Single address Single address Not available
mode
mode
Not available
External
memory
Single address Dual address Dual address Dual address Dual address
mode
mode
mode
mode
mode
Memory-
mapped
external
device
Single address Dual address Dual address Dual address Dual address
mode
mode
mode
mode
mode
On-chip
memory
Not available Dual address Dual address Dual address Dual address
mode
mode
mode
mode
On-chip
peripheral
module
Not available
Dual address
mode
Dual address
mode
Dual address
mode
Dual address
mode
Note: The dual address mode includes direct address mode and indirect address mode.
Rev. 5.00 Jan 06, 2006 page 158 of 818
REJ09B0273-0500