SH7050 Datasheet, PDF (163/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
9.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
DMA channel control registers 0–3 (CHCR0–CHCR3) is a 32-bit read/write register where the
operation and transmission of each channel is designated. Bits 31–21 and bit 7 should always read
0. The written value should also be 0. They are initialized to 0 by a power-on reset and in standby
mode.
Bit: 31
30
29
28
27
26
25
24
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
—
—
—
DI
RO
RL
AM
AL
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
DM1 DM0 SM1 SM0 RS3 RS2 RS1 RS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
—
DS
TM
TS1 TS0
IE
TE
DE
Initial value: 0
R/W: R
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/(W)^* R/W
Notes: 1. TE bit: Allows only 0 write after reading 1.
2. The DI, RO, RL, AM, AL, or DS bit may be absent, depending on the channel.
Bit 20—Direct/Indirect (DI): Specifies either direct address mode operation or indirect address
mode operation for channel 3 source address. This bit is valid only in CHCR3. It always reads 0
for CHCR0–CHCR2, and cannot be modified.
Bit 20: DI
0
1
Description
Direct access mode operation for channel 3 (initial value)
Indirect access mode operation for channel 3
Rev. 5.00 Jan 06, 2006 page 143 of 818
REJ09B0273-0500