SH7050 Datasheet, PDF (106/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 6 Interrupt Controller (INTC)
6.3.2 Interrupt Control Register (ICR)
The ICR is a 16-bit register that sets the input signal detection mode of the external interrupt input
pin NMI and IRQ0 –IRQ7 and indicates the input signal level to the NMI pin. A power-on reset
and hardware standby mode initialize ICR but the software standby mode does not.
Bit: 15
14
13
12
11
10
9
8
NMIL
—
—
—
—
—
—
NMIE
Initial value: *
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 7
6
5
4
3
IRQ0S IRQ1S IRQ2S IRQ3S IRQ4S
Initial value: 0
0
0
0
0
R/W: R/W R/W R/W R/W R/W
Note: * When NMI input is high: 1; when NMI input is low: 0
2
IRQ5S
0
R/W
1
IRQ6S
0
R/W
0
IRQ7S
0
R/W
Bit 15—NMI Input Level (NMIL): Sets the level of the signal input at the NMI pin. This bit can
be read to determine the NMI pin level. This bit cannot be modified.
Bit 15: NMIL
0
1
Description
NMI input level is low
NMI input level is high
Bits 14 to 9—Reserved: These bits always read as 0. The write value should always be 0.
Bit 8—NMI Edge Select (NMIE)
Bit 8: NMIE
0
1
Description
Interrupt request is detected on falling edge of NMI input (initial value)
Interrupt request is detected on rising edge of NMI input
Rev. 5.00 Jan 06, 2006 page 86 of 818
REJ09B0273-0500