SH7050 Datasheet, PDF (338/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Sample Setup Procedure for Waveform Output by Output Compare-Match: An example of
the setup procedure for waveform output by output compare-match is shown in figure 10.46.
1. Set the first-stage counter clock φ' in prescaler register 1 (PSCR1), and select the second-stage
counter clock φ" with the CKSEL bit in the timer control register (TCR). When selecting an
external clock, also select the external clock edge type with the CKEG bit in TCR.
2. Set the port E control register (PECR) or port G control register (PGCR), corresponding to the
waveform output port, to ATU output compare-match output. Also set the corresponding bit to
1 in the port E IO register (PEIOR) or port G IO register (PGIOR) to specify the output
attribute for the port.
3. Select 0, 1, or toggle output for output compare-match output with the timer I/O control
register (TIOR). If necessary, an interrupt request can be sent to the CPU on output compare-
match by making the appropriate setting in the interrupt enable register (TIER).
4. Set the timing for compare-match generation in the ATU general register (GR) corresponding
to the port set in 2.
5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running
counter (TCNT). Waveform output is performed from the relevant port when the TCNT value
and GR value match.
Rev. 5.00 Jan 06, 2006 page 318 of 818
REJ09B0273-0500