SH7050 Datasheet, PDF (251/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
TIOR4A
Bit:
Initial value:
R/W:
7
CCI4B
0
R/W
6
IO4B2
0
R/W
5
IO4B1
0
R/W
4
IO4B0
0
R/W
3
CCI4A
0
R/W
2
IO4A2
0
R/W
1
IO4A1
0
R/W
0
IO4A0
0
R/W
TIOR4B
Bit:
Initial value:
R/W:
7
CCI4D
0
R/W
6
IO4D2
0
R/W
5
IO4D1
0
R/W
4
IO4D0
0
R/W
3
CCI4C
0
R/W
2
IO4C2
0
R/W
1
IO4C1
0
R/W
0
IO4C0
0
R/W
TIOR4A and TIOR4B are 8-bit readable/writable registers. When bit 1 of TMDR is 0, they
specify whether general registers GR4A to GR4D are used as input capture or compare-match
registers, and also perform edge detection and output value setting. Also, when bit 1 of TMDR is
0, they select enabling or disabling of free-running counter (TCNT4) clearing.
Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
TIOR5A
Bit:
Initial value:
R/W:
7
CCI5B
0
R/W
6
IO5B2
0
R/W
5
IO5B1
0
R/W
4
IO5B0
0
R/W
3
CCI5A
0
R/W
2
IO5A2
0
R/W
1
IO5A1
0
R/W
0
IO5A0
0
R/W
TIOR5A is an 8-bit readable/writable register. When bit 2 of TMDR is 0, it specifies whether
general registers GR5A and GR5B are used as input capture or compare-match registers, and also
performs edge detection and output value setting. Also, when bit 2 of TMDR is 0, TIOR5A selects
enabling or disabling of free-running counter (TCNT5) clearing.
TIOR5A is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Rev. 5.00 Jan 06, 2006 page 231 of 818
REJ09B0273-0500