SH7050 Datasheet, PDF (258/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 4:
OVF0
0
1
Description
[Clearing condition]
When OVF0 is read while set to 1, then 0 is written in OVF0
[Setting condition]
When the TCNT0 value overflows (from H'FFFFFFFF to H'00000000)
(Initial value)
Bit 3—Input Capture Flag (ICF0D): Status flag that indicates ICR0D input capture.
Bit 3:
ICF0D
0
1
Description
[Clearing condition]
(Initial value)
When ICF0D is read while set to 1, then 0 is written in ICF0D
[Setting condition]
When the TCNT0 value is transferred to the input capture register (ICR0D) by an input
capture signal
Bit 2—Input Capture Flag (ICF0C): Status flag that indicates ICR0C input capture.
Bit 2:
ICF0C
0
1
Description
[Clearing condition]
(Initial value)
When ICF0C is read while set to 1, then 0 is written in ICF0C
[Setting condition]
When the TCNT0 value is transferred to the input capture register (ICR0C) by an input
capture signal
Bit 1—Input Capture Flag (ICF0B): Status flag that indicates ICR0B input capture.
Bit 1:
ICF0B
0
1
Description
[Clearing condition]
(Initial value)
When ICF0B is read while set to 1, then 0 is written in ICF0B
[Setting condition]
When the TCNT0 value is transferred to the input capture register (ICR0B) by an input
capture signal
Rev. 5.00 Jan 06, 2006 page 238 of 818
REJ09B0273-0500