SH7050 Datasheet, PDF (16/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

16.3.12 Port F Control Registers 1 and 2 (PFCR1, PFCR2) ............................................. 504
16.3.13 Port G IO Register (PGIOR) ................................................................................ 510
16.3.14 Port G Control Registers 1 and 2 (PGCR1, PGCR2) ........................................... 510
16.3.15 CK Control Register (CKCR) .............................................................................. 516
Section 17 I/O Ports (I/O) ................................................................................................. 517
17.1 Overview........................................................................................................................... 517
17.2 Port A................................................................................................................................ 517
17.2.1 Register Configuration......................................................................................... 518
17.2.2 Port A Data Register (PADR) .............................................................................. 518
17.3 Port B ................................................................................................................................ 519
17.3.1 Register Configuration......................................................................................... 520
17.3.2 Port B Data Register (PBDR) .............................................................................. 520
17.4 Port C ................................................................................................................................ 522
17.4.1 Register Configuration......................................................................................... 522
17.4.2 Port C Data Register (PCDR) .............................................................................. 523
17.5 Port D................................................................................................................................ 524
17.5.1 Register Configuration......................................................................................... 525
17.5.2 Port D Data Register (PDDR) .............................................................................. 525
17.6 Port E ................................................................................................................................ 527
17.6.1 Register Configuration......................................................................................... 527
17.6.2 Port E Data Register (PEDR)............................................................................... 528
17.7 Port F................................................................................................................................. 529
17.7.1 Register Configuration......................................................................................... 529
17.7.2 Port F Data Register (PFDR) ............................................................................... 530
17.8 Port G................................................................................................................................ 531
17.8.1 Register Configuration......................................................................................... 531
17.8.2 Port G Data Register (PGDR) .............................................................................. 532
17.9 Port H................................................................................................................................ 533
17.9.1 Register Configuration......................................................................................... 533
17.9.2 Port H Data Register (PHDR) .............................................................................. 534
17.10 POD (Port Output Disable) ............................................................................................... 534
Section 18 ROM (128 kB Version)................................................................................ 535
18.1 Features ............................................................................................................................. 535
18.2 Overview........................................................................................................................... 536
18.2.1 Block Diagram ..................................................................................................... 536
18.2.2 Mode Transitions ................................................................................................. 537
18.2.3 On-Board Programming Modes........................................................................... 538
18.2.4 Flash Memory Emulation in RAM ...................................................................... 540
18.2.5 Differences between Boot Mode and User Program Mode ................................. 541
Rev. 5.00 Jan 06, 2006 page xvi of xx