SH7050 Datasheet, PDF (196/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Burst Mode, Dual Address, and Level Detection: DREQ sampling timing in burst mode with
dual address and level detection is virtually the same as that of cycle steal mode.
For example, DMAC transfer begins (figure 9.19), at the earliest, three cycles after the timing of
the first sampling. The second sampling also begins from the start of the transfer one bus cycle
before the start of the first DMAC transfer. In burst mode, as long as transfer requests are issued,
DMAC transfer continues. Therefore, the “transfer one bus cycle before the start of the DMAC
transfer” may be a DMAC transfer.
In burst mode, the DACK output period is thesame as that of cycle steal mode. Figure 9.20 shows
the normal operation of this burst mode.
Rev. 5.00 Jan 06, 2006 page 176 of 818
REJ09B0273-0500