SH7050 Datasheet, PDF (220/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
10.1.2 Block Diagrams
Overall block Diagram ATU Block Diagram: Figure 10.1 shows an overall block diagram of
the ATU.
TCLKA
TCLKB
IC/OC control
I/O interrupt
control
Counter and register control,
and comparator
Interrupts
Inter-module
connection
signals
External pins
Inter-module
address bus
........
φ
Module data bus
Inter-module
data bus
Legend:
TSTR: Timer start register (16 bits)
Interrupts:
ITV0–ITV3, OV10–OV15, IC10A –IC10D, IMI1A–IMI1F, IMI2A, IMI2B, IMI3A–IMI3D,
IMI4A–IMI4D, IMI5A, IMI5B, CMI6–CMI9, OSI10A–OSI10H
External pins:
TIA0–TID0, TIOA1–TIOF1, TIOA2, TIOIB2, TIOA3–TIOD3, TIOA4–TIOD3, TIOA5, TIOB5,
TO6–TO9, TOA10–TOH10
Inter-module connection signals:
Signals to A/D converter, signals to direct memory access controller (DMAC),
signals to advanced pulse controller (APC)
Figure 10.1 Overall Block Diagram of ATU
Rev. 5.00 Jan 06, 2006 page 200 of 818
REJ09B0273-0500