SH7050 Datasheet, PDF (805/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
A/D Control/Status Register 0
(ADCSR0)
H'FFFF85E8
8/16
A/D
Bit: 7
6
5
4
Bit name: ADF ADIE ADM1 ADM0
Initial value: 0
0
0
0
R/W: R/(W)* R/W R/W R/W
Note: * Only 0 can be written to clear the flag.
3
CH3
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
0
CH0
0
R/W
Bit
Bit Name
Value
Description
7
A/D end flag (ADF) 0
A/D0 executing A/D conversion or in idle state (Initial value)
[Clearing conditions]
1. Read ADF when ADF =1, then write 0 in ADF
2. DMAC activated by ADI0 interrupt
1
A/D0 has ended A/D conversion and digital value has been transferred to
ADDR
[Setting conditions]
1. Single mode: A/D conversion ends
2. Scan mode: All A/D conversion ends within one selected analog group
6
A/D interrupt enable 0
(ADIE)
1
ADI0 A/D interrupt is disabled
ADI0 A/D interrupt is enabled
(Initial value)
5, 4
A/D mode 1 and 0 0 0
(ADM1, ADM0)
1
Single mode
4-channel scan mode (analog group 0/group 1/group 2)
10
8-channel scan mode (analog groups 0 and 1)
1
12-channel scan mode (analog groups 0, 1, and 2)
3, 2,
Channel select 3 to 0
1, 0
(CH3 to CH0)
Single Mode
Analog Input Channels
4-Channel
Scan Mode
8-Channel
Scan Mode
12-Channel
Scan Mode
0 0 0 0 AN0
AN0
(Initial value)
AN0, 4
AN0, 4, 8
1 AN1
AN0, 1
AN0, 1, 4, 5
AN0, 1, 4, 5, 8, 9
1 0 AN2
AN0–2
AN0–2, 4–6
AN0–2, 4–6,
8–10
1 AN3
AN0–3
AN0–7
AN0–11
1 0 0 AN4
AN4
AN0, 4
AN0, 4, 8
1 AN5
AN4, 5
AN0, 1, 4, 5
AN0, 1, 4, 5, 8, 9
1 0 AN6
AN4–6
AN0–2, 4–6
AN0–2, 4–6,
8–10
1 AN7
1 0*¹ 0 0 AN8
AN4–7
AN8
AN0–7
Reserved*²
AN0–11
AN0, 4, 8
1 AN9
AN8, 9
AN0, 1, 4, 5, 8, 9
1 0 AN10
AN8–10
AN0–2, 4–6, 8–10
1 AN11
AN8–11
AN0–11
Notes: 1. Must be cleared to 0.
2. Reserved for future expansion. Do not use these settings.
Rev. 5.00 Jan 06, 2006 page 785 of 818
REJ09B0273-0500