SH7050 Datasheet, PDF (550/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 17 I/O Ports (I/O)
17.7.2 Port F Data Register (PFDR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
—
—
—
—
PF11 PF10 PF9
DR DR DR
PF8
DR
PF7
DR
PF6
DR
PF5
DR
PF4
DR
PF3
DR
PF2
DR
PF1
DR
PF0
DR
Initial value: 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The port F data register (PFDR) is a 16-bit readable/writable register that stores port F data. Bits
PF11DR to PF0DR correspond to pins PF11/BREQ/PULS7 to PF0/IRQ0.
When a pin functions as a general output, if a value is written to PFDR, that value is output
directly from the pin, and if PFDR is read, the register value is returned directly regardless of the
pin state.
When a pin functions as a general input, if PFDR is read the pin state, not the register value, is
returned directly. If a value is written to PFDR, although that value is written into PFDR it does
not affect the pin state. Table 17.12 summarizes port F data register read/write operations.
PFDR is initialized by a power-on reset (excluding a WDT power-on reset), and in hardware
standby mode. It is not initialized in software standby mode or sleep mode.
Table 17.12 Port F Data Register (PFDR) Read/Write Operations
PFIOR
0
1
Pin Function
General input
Other than general
input
General output
Other than general
output
Read
Pin state
Pin state
PFDR value
PFDR value
Write
Value is written to PFDR, but does not affect
pin state
Value is written to PFDR, but does not affect
pin state
Write value is output from pin
Value is written to PFDR, but does not affect
pin state
Rev. 5.00 Jan 06, 2006 page 530 of 818
REJ09B0273-0500