SH7050 Datasheet, PDF (462/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 14 A/D Converter
14.2.3 A/D Control Register 0 (ADCR0)
A/D control register 0 (ADCR0) is an 8-bit readable/writable register that controls the start of A/D
conversion and selects the operating clock.
ADCR0 is initialized to H'1F by a power-on reset, and in hardware standby mode and software
standby mode.
Bits 4 to 0 of ADCR0 are reserved. These bits cannot be written to, and always return 1 if read.
Bit: 7
6
5
4
3
2
1
0
TRGE CKS ADST —
—
—
—
—
Initial value: 0
0
0
1
1
1
1
1
R/W: R/W R/W R/W
R
R
R
R
R
Bit 7—Trigger Enable (TRGE): Enables or disables triggering of A/D conversion by external
input or the ATU.
Bit 7:
TRGE
0
1
Description
A/D conversion triggering by external input or ATU is disabled
A/D conversion triggering by external input or ATU is enabled
(Initial value)
For details of external or ATU trigger selection, see section 14.2.6, A/D Trigger Register.
When ATU triggering is selected, clear bit 7 of the ADTRGR register to 0.
When external triggering is selected, upon input of a low-level pulse to the ADTRG pin after
TRGE has been set to 1, the A/D converter detects the falling edge of the pulse, and sets the
ADST bit to 1 in ADCR. The same operation is subsequently performed when 1 is written in the
ADST bit by software. External triggering of A/D conversion is only enabled when the ADST bit
is cleared to 0.
When external triggering is used, the low-level pulse input to the ADTRG pin must be at least 1.5
φ clock cycles in width. For details, see section 14.4.4, External Triggering of A/D Conversion.
Rev. 5.00 Jan 06, 2006 page 442 of 818
REJ09B0273-0500