SH7050 Datasheet, PDF (636/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 19 ROM (256 kB Version)
19.8.2 Software Protection
Software protection can be implemented by setting erase block register 1 (EBR1), erase block
register 2 (EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software
protection is in effect, setting the P1 or E1 bit in flash memory control register 1 (FLMCR1), or
the P2 or E2 bit in flash memory control register 2 (FLMCR2), does not cause a transition to
program mode or erase mode. (See table 19.8.)
Table 19.8 Software Protection
Item
Description
SWE pin protection
• Clearing the SWE bit to 0 in FLMCR1 sets
the program/erase-protected state for all
blocks.
• (Execute in on-chip RAM or external
memory.)
Block specification
protection
• Erase protection can be set for individual
blocks by settings in erase block register 1
(EBR1) and erase block register 2
(EBR2).
• Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-protected state.
Emulation protection •
Setting the RAMS bit to 1 in the RAM
emulation register (RAMER) places all
blocks in the program/erase-protected
state.
Functions
Program Erase
Yes
Yes
—
Yes
Yes
Yes
Rev. 5.00 Jan 06, 2006 page 616 of 818
REJ09B0273-0500