SH7050 Datasheet, PDF (193/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Figures 9.17 and 9.18 show cycle steal mode and single address mode. In this case, transfer begins
at earliest three cycles after the first DREQ sampling. The second sampling begins from the start
of the transfer one bus cycle before the start of the first DMAC transfer. In single address mode,
the DACK signal is output during the DMAC transfer period.
Rev. 5.00 Jan 06, 2006 page 173 of 818
REJ09B0273-0500