SH7050 Datasheet, PDF (749/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Timer Status Register C (TSRC)
H'FFFF82C9 (Channel 2) 8
ATU
Bit: 7
6
5
4
Bit name: —
—
—
—
Initial value: 0
0
0
0
R/W: R
R
R
R
Note: * Only 0 can be written to clear the flag.
3
2
1
0
—
OVF2 IMF2B IMF2A
0
0
0
0
R R/(W)* R/(W)* R/(W)*
Bit
Bit Name
Value Description
2
Overflow flag (OVF2)
0
[Clearing condition]
(Initial value)
Read OVF2 when OVF2 =1, then write 0 in OVF2
1
[Setting condition]
TCNT2 overflowed from H'FFFF to H'0000
1
Input capture/compare 0
[Clearing condition]
(Initial value)
match flag (IMF2B)
Read IMF2B when IMF2B =1, then write 0 in
IMF2B
1
[Setting conditions]
1. TCNT2 value is transferred to GR2B by an
input capture signal when GR2B functions as
an input capture register
2. TCNT2 = GR2B when GR2B functions as an
output compare register
0
Input capture/compare 0
[Clearing condition]
(Initial value)
match flag (IMF2A)
Read IMF2A when IMF2A =1, then write 0 in
IMF2A
1
[Setting conditions]
1. TCNT2 value is transferred to GR2A by an
input capture signal when GR2A functions as
an input capture register
2. TCNT2 = GR2A when GR2A functions as an
output compare register
Rev. 5.00 Jan 06, 2006 page 729 of 818
REJ09B0273-0500