SH7050 Datasheet, PDF (262/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Timer Status Register C (TSRC)
TSRC indicates the status of channel 2 input capture, compare-match, and overflow.
Bit: 7
6
5
4
—
—
—
—
Initial value: 0
0
0
0
R/W: R
R
R
R
Note: * Only 0 can be written, to clear the flag.
3
2
1
0
—
OVF2 IMF2B IMF2A
0
0
0
0
R R/(W)* R/(W)* R/(W)*
Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2—Overflow Flag (OVF2): Status flag that indicates TCNT2 overflow.
Bit 2:
OVF2
0
1
Description
[Clearing condition]
When OVF2 is read while set to 1, then 0 is written in OVF2
[Setting condition]
When the TCNT2 value overflows (from H'FFFF to H'0000)
(Initial value)
Bit 1—Input Capture/Compare-Match Flag (IMF2B): Status flag that indicates GR2B input
capture or compare-match.
Bit 1:
IMF2B
0
1
Description
[Clearing condition]
(Initial value)
When IMF2B is read while set to 1, then 0 is written in IMF2B
[Setting conditions]
• When the TCNT2 value is transferred to GR2B by an input capture signal while
GR2B is functioning as an input capture register
• When TCNT2 = GR2B while GR2B is functioning as an output compare register
Rev. 5.00 Jan 06, 2006 page 242 of 818
REJ09B0273-0500